1. Field of Invention
This invention relates to computer program development and, more particularly, to the use of a code breakpoint manipulated by a user to extract information on which instructions within various stages of a superscalar microprocessor pipeline will progress to succeeding stages during a particular moment in time (i.e., clock cycle), in order to possibly modify the pipeline sequence for enhancing microprocessor instruction throughput.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A typical microprocessor or “processor” involves various functional units that receive instructions from, for example, memory and operate on those instructions to produce results stored back into the memory or dispatched to an input/output device. There are many types of processors available in the market. For example, processors can be classified as either CISC or RISC processors. In addition, processors can implement multiple stages in a pipeline and can implement, possibly, numerous pipelines through the functional units.
Depending on how the pipeline is configured, it is generally desirable to arrange the instruction addresses of the program in a particular sequence. If properly sequenced, the instructions can be carried out as steps which proceed as successive stages through the pipeline to produce an efficient instruction throughput. In order to enhance throughput, it is often desirable to implement multiple pipelines in parallel so that two or more instructions can be fed through the functional units simultaneously. Placing multiple instructions through a pipeline in unison (i.e., during the same clock cycle) is generally known as “superscalar,” and processors which employ the superscalar concept are known as superscalar processors.
A problem inherent to pipelined processors and especially superscalar processors is the data/procedural dependencies and resource conflicts that will occur when attempting to execute instructions in a given sequence. For example, data dependency will exist if a superscalar processor attempts to execute two instructions at the same time when, in fact, the execution of the second instruction should be delayed until the first instruction produces its value. In addition to data dependencies, superscalar processors also encounter procedural dependencies that often occur whenever the instruction sequence encounters a branch instruction. For example, instructions which follow a given branch instruction have a procedural dependency on each branch that has been executed up to that point. In addition, resource conflicts arise in superscalar processors when two instructions must use the same resource at the same time (e.g., two instructions being fetched or executed within the same clock cycle).
Attempts have been made to resolve many of the inherent dependencies and conflicts that arise in superscalar processors. For example, such processors might use look-ahead buffers, prefetch buffers, and reorder buffers in an attempt to adjust the sequence at which instructions are dispatched to the various functional units. This form of reordering typically occurs within the hardware elements of the processor itself. Other techniques might involve actually rewriting the object code before the code is stored in the memory device associated with the processor.
In the latter instance in which software is rewritten, many tools might be used during development of the software to optimize the sequencing of the instructions. These tools will take into account the particular architecture of the processor involved and, thereby, arrange the instruction sequence so that the throughput of instructions within the pipeline is maximized. These tools are often referred to as “integrated development tools” which are used to configure, build, and debug programs used by a particular processor.
As the software is being developed, the debugging feature will often schedule the sequence of instructions without attention paid to the pipeline structure of the processor. Unfortunately, a developer using such a tool cannot readily modify the sequence of instructions depending on where an instruction exists within the processor pipeline at any given time. Absent being able to visualize the whereabouts of each instruction within a pipeline, a developer will be unable to optimize the pipeline throughput. Even further, absent any way to visualize whether a particular instruction will progress to the next stage in the pipeline, a developer cannot know whether the pipeline flow is optimized.